Commit fe8ad73c authored by Tomasz Zawadzki's avatar Tomasz Zawadzki Committed by Tomasz Zawadzki
Browse files

ut/nvme: clean nvme registers before every UT 



Prevents needing to reset registers for relevant tests.

Note that shst is checked on every controller destruction
and needs to be set appropriately to succeed.

Change-Id: I86978bd534b1f846671d24c6b619a40a66145e2f
Signed-off-by: default avatarTomasz Zawadzki <tomasz.zawadzki@nutanix.com>
Reviewed-on: https://review.spdk.io/c/spdk/spdk/+/26355


Community-CI: Mellanox Build Bot
Tested-by: default avatarSPDK Automated Test System <spdkbot@gmail.com>
Reviewed-by: default avatarKonrad Sztyber <ksztyber@nvidia.com>
Reviewed-by: default avatarJim Harris <jim.harris@nvidia.com>
parent c77d4d5b

test/unit/lib/nvme/nvme_ctrlr.c/nvme_ctrlr_ut.c

+6 −38
Original line number Diff line number Diff line
@@ -771,8 +771,6 @@ test_nvme_ctrlr_init_en_1_rdy_0(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 1, CSTS.RDY = 0

	 */
@@ -834,7 +832,6 @@ test_nvme_ctrlr_init_en_1_rdy_0(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -843,8 +840,6 @@ test_nvme_ctrlr_init_en_1_rdy_1(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 1, CSTS.RDY = 1

	 * init() should set CC.EN = 0.
@@ -897,7 +892,6 @@ test_nvme_ctrlr_init_en_1_rdy_1(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -906,8 +900,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 0, CSTS.RDY = 0

	 * init() should set CC.EN = 1.
@@ -948,7 +940,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -981,7 +972,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1014,7 +1004,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1047,7 +1036,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1094,7 +1082,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -1103,8 +1090,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 0, CSTS.RDY = 0

	 * init() should set CC.EN = 1.
@@ -1145,7 +1130,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1181,7 +1165,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1214,7 +1197,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1247,7 +1229,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1294,7 +1275,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}

static void
@@ -1302,8 +1282,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 0, CSTS.RDY = 0

	 * init() should set CC.EN = 1.
@@ -1344,7 +1322,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1377,7 +1354,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1413,7 +1389,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1446,7 +1421,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	/*

	 * Complete and destroy the controller

	 */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);



	/*
@@ -1493,7 +1467,6 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -1502,8 +1475,6 @@ test_nvme_ctrlr_init_en_0_rdy_0(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 0, CSTS.RDY = 0

	 * init() should set CC.EN = 1.
@@ -1545,7 +1516,6 @@ test_nvme_ctrlr_init_en_0_rdy_0(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -1554,8 +1524,6 @@ test_nvme_ctrlr_init_en_0_rdy_1(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 0, CSTS.RDY = 1

	 */
@@ -1606,7 +1574,6 @@ test_nvme_ctrlr_init_en_0_rdy_1(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -2345,8 +2312,6 @@ test_nvme_ctrlr_init_delay(void) 
{

	DECLARE_AND_CONSTRUCT_CTRLR();



	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));



	/*

	 * Initial state: CC.EN = 0, CSTS.RDY = 0

	 * init() should set CC.EN = 1.
@@ -2405,7 +2370,6 @@ test_nvme_ctrlr_init_delay(void) 
		nvme_ctrlr_process_init(&ctrlr);

	}



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -2968,7 +2932,6 @@ test_nvme_ctrlr_reset(void) 
	CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL);

	CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2));



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -3552,7 +3515,6 @@ test_nvme_ctrlr_disable(void) 
	CU_ASSERT(rc == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);



	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;

	nvme_ctrlr_destruct(&ctrlr);

}
@@ -3575,6 +3537,12 @@ test_nvme_numa_id(void) 
static void

ut_setup(void)

{

	/* Registers are set as needed during UT, clear them. */

	memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs));

	/* This is checked during every nvme_ctrlr_destruct(),

	 * just mark it as complete always. */

	g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE;



	g_set_reg_cb = NULL;



	set_size = 1;