Commit dcfbafeb authored by Barry Spinney's avatar Barry Spinney Committed by Daniel Verkamp
Browse files

barrier: add proper barrier instructions for ARM 64 



Add code to implement the write memory barrier and read/write memory
barrier for ARM 64 platforms.

Change-Id: I8b63db25ba1f70a729874ca143db13501d976676
Signed-off-by: default avatarBarry Spinney <spinney@mellanox.com>
Reviewed-on: https://review.gerrithub.io/386534


Reviewed-by: default avatarDaniel Verkamp <daniel.verkamp@intel.com>
Tested-by: default avatarSPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarBen Walker <benjamin.walker@intel.com>
parent 0c06e1ea

include/spdk/barrier.h

+4 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ extern "C" { 
/** Write memory barrier */

#ifdef __PPC64__

#define spdk_wmb()	__asm volatile("sync" ::: "memory")

#elif defined(__aarch64__)

#define spdk_wmb()	__asm volatile("dsb st" ::: "memory")

#elif defined(__i386__) || defined(__x86_64__)

#define spdk_wmb()	__asm volatile("sfence" ::: "memory")

#else
@@ -61,6 +63,8 @@ extern "C" { 
/** Full read/write memory barrier */

#ifdef __PPC64__

#define spdk_mb()	__asm volatile("sync" ::: "memory")

#elif defined(__aarch64__)

#define spdk_mb()	__asm volatile("dsb sy" ::: "memory")

#elif defined(__i386__) || defined(__x86_64__)

#define spdk_mb()	__asm volatile("mfence" ::: "memory")

#else