Commit dc61452d authored by h00448672's avatar h00448672 Committed by Darek Stojaczyk
Browse files

nvme: Modify the memory barrier mode to improve performance 



The mode of dmb oshld can guarantees cpu sequential execution,
which has less impact on performance.

Change-Id: If30b6a682a2216eecd1da039267ed4f5471afc38
Signed-off-by: default avatarh00448672 <heyang18@huawei.com>
Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/446827


Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: default avatarDarek Stojaczyk <dariusz.stojaczyk@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
parent 9e2eb8cb

lib/nvme/nvme_pcie.c

+3 −1
Original line number Diff line number Diff line
@@ -2139,13 +2139,15 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_ 
		if (cpl->status.p != pqpair->flags.phase) {

			break;

		}

#if defined(__PPC64__) || defined(__aarch64__)

#ifdef __PPC64__

		/*

		 * This memory barrier prevents reordering of:

		 * - load after store from/to tr

		 * - load after load cpl phase and cpl cid

		 */

		spdk_mb();

#elif defined(__aarch64__)

		__asm volatile("dmb oshld" ::: "memory");

#endif



		if (spdk_unlikely(++pqpair->cq_head == pqpair->num_entries)) {