Commit c65210d0 authored by GangCao's avatar GangCao
Browse files

nvme: return error immediately when enabling controller failed 



Change-Id: Id9cf6873cc831bd5099df49db95ef5073badf461
Signed-off-by: default avatarGangCao <gang.cao@intel.com>
parent 7fea4151

lib/nvme/nvme_ctrlr.c

+4 −4
Original line number Diff line number Diff line
@@ -864,9 +864,9 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) 
			/*

			 * Controller is currently disabled. We can jump straight to enabling it.

			 */

			nvme_ctrlr_enable(ctrlr);

			rc = nvme_ctrlr_enable(ctrlr);

			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);

			return 0;

			return rc;

		}

		break;
@@ -883,9 +883,9 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) 
	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:

		if (csts.bits.rdy == 0) {

			/* CC.EN = 0 && CSTS.RDY = 0, so we can enable the controller now. */

			nvme_ctrlr_enable(ctrlr);

			rc = nvme_ctrlr_enable(ctrlr);

			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);

			return 0;

			return rc;

		}

		break;

test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c

+7 −7
Original line number Diff line number Diff line
@@ -455,7 +455,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -473,7 +473,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -491,7 +491,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -593,7 +593,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -611,7 +611,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -692,7 +692,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -730,7 +730,7 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);