Commit 962fdadf authored by Dariusz Stojaczyk's avatar Dariusz Stojaczyk Committed by Jim Harris
Browse files

barrier: added spdk_smp_*mb to sync between cores 



The smp variants of memory barriers can
be used in cases where the sequential
order of loads/stores is required just
between CPU cores.

Change-Id: Ifbd187338bb441d4563672fa2f2afbe666607d76
Signed-off-by: default avatarDariusz Stojaczyk <dariuszx.stojaczyk@intel.com>
Reviewed-on: https://review.gerrithub.io/388765


Reviewed-by: default avatarBen Walker <benjamin.walker@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Tested-by: default avatarSPDK Automated Test System <sys_sgsw@intel.com>
parent 3b2ed0e9

include/spdk/barrier.h

+36 −0
Original line number Diff line number Diff line
@@ -72,6 +72,42 @@ extern "C" { 
#error Unknown architecture

#endif



/** SMP read memory barrier. */

#ifdef __PPC64__

#define spdk_smp_rmb()	__asm volatile("lwsync" ::: "memory")

#elif defined(__aarch64__)

#define spdk_smp_rmb()	__asm volatile("dmb ishld" ::: "memory")

#elif defined(__i386__) || defined(__x86_64__)

#define spdk_smp_rmb()	spdk_compiler_barrier()

#else

#define spdk_smp_rmb()

#error Unknown architecture

#endif



/** SMP write memory barrier. */

#ifdef __PPC64__

#define spdk_smp_wmb()	__asm volatile("lwsync" ::: "memory")

#elif defined(__aarch64__)

#define spdk_smp_wmb()	__asm volatile("dmb ishst" ::: "memory")

#elif defined(__i386__) || defined(__x86_64__)

#define spdk_smp_wmb()	spdk_compiler_barrier()

#else

#define spdk_smp_wmb()

#error Unknown architecture

#endif



/** SMP read/write memory barrier. */

#ifdef __PPC64__

#define spdk_smp_mb()	spdk_mb()

#elif defined(__aarch64__)

#define spdk_smp_mb()	__asm volatile("dmb ish" ::: "memory")

#elif defined(__i386__) || defined(__x86_64__)

#define spdk_smp_mb()	spdk_mb()

#else

#define spdk_smp_mb()

#error Unknown architecture

#endif



#ifdef __cplusplus

}

#endif