Commit 8cb09df6 authored by Daniel Verkamp's avatar Daniel Verkamp
Browse files

pci_ids: add SPDK_ prefix 



PCI_VENDOR_ID_INTEL -> SPDK_PCI_VID_INTEL

Also change the inclusion guard macro to be consistent with the other
SPDK headers.

Change-Id: I29346267172cb8c07cc4289eed4eca2d55e942d6
Signed-off-by: default avatarDaniel Verkamp <daniel.verkamp@intel.com>
parent 87844a30

examples/nvme/identify/identify.c

+1 −1
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ get_log_pages(struct nvme_controller *ctrlr) 
	}



	ctrlr_data = nvme_ctrlr_get_data(ctrlr);

	if (ctrlr_data->vid == PCI_VENDOR_ID_INTEL) {

	if (ctrlr_data->vid == SPDK_PCI_VID_INTEL) {

		if (nvme_ctrlr_is_log_page_supported(ctrlr, NVME_INTEL_LOG_SMART)) {

			if (get_intel_smart_log_page(ctrlr) == 0) {

				outstanding_commands++;

include/spdk/pci_ids.h

+4 −4
Original line number Diff line number Diff line
@@ -31,11 +31,11 @@ 
 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef __PCI_IDS_H__

#define __PCI_IDS_H__

#ifndef SPDK_PCI_IDS

#define SPDK_PCI_IDS



#include <stdint.h>



#define PCI_VENDOR_ID_INTEL		0x8086

#define SPDK_PCI_VID_INTEL		0x8086



#endif /* __PCI_IDS_H__ */
 
#endif /* SPDK_PCI_IDS */

lib/ioat/ioat_impl.h

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ ioat_zmalloc(const char *tag, size_t size, unsigned align, uint64_t *phys_addr) 
static inline bool

ioat_pci_device_match_id(uint16_t vendor_id, uint16_t device_id)

{

	if (vendor_id != PCI_VENDOR_ID_INTEL) {

	if (vendor_id != SPDK_PCI_VID_INTEL) {

		return false;

	}

lib/nvme/nvme_ctrlr.c

+3 −3
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ nvme_ctrlr_construct_intel_support_log_page_list(struct nvme_controller *ctrlr, 
	struct spdk_pci_device *dev;

	struct pci_id pci_id;



	if (ctrlr->cdata.vid != PCI_VENDOR_ID_INTEL || log_page_directory == NULL)

	if (ctrlr->cdata.vid != SPDK_PCI_VID_INTEL || log_page_directory == NULL)

		return;



	dev = ctrlr->devhandle;
@@ -120,7 +120,7 @@ nvme_ctrlr_set_supported_log_pages(struct nvme_controller *ctrlr) 
	if (ctrlr->cdata.lpa.celp) {

		ctrlr->log_page_supported[NVME_LOG_COMMAND_EFFECTS_LOG] = true;

	}

	if (ctrlr->cdata.vid == PCI_VENDOR_ID_INTEL) {

	if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {

		nvme_ctrlr_set_intel_support_log_pages(ctrlr);

	}

}
@@ -161,7 +161,7 @@ nvme_ctrlr_set_supported_features(struct nvme_controller *ctrlr) 
	if (ctrlr->cdata.hmpre) {

		ctrlr->feature_supported[NVME_FEAT_HOST_MEM_BUFFER] = true;

	}

	if (ctrlr->cdata.vid == PCI_VENDOR_ID_INTEL) {

	if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {

		nvme_ctrlr_set_intel_supported_features(ctrlr);

	}

}

lib/nvme/nvme_intel.c

+6 −6
Original line number Diff line number Diff line
@@ -42,12 +42,12 @@ struct nvme_intel_quirk { 
};



static const struct nvme_intel_quirk intel_p3x00[] = {

	{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{PCI_VENDOR_ID_INTEL, 0x0953, PCI_VENDOR_ID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{0x0000, 0x0000, 0x0000, 0x0000}, 0												}

};