Commit 8a9c1d40 authored by Ben Walker's avatar Ben Walker Committed by Daniel Verkamp
Browse files

nvme: Make striping a quirk 



Use the standard quirk mechanism to specify which devices
need software assisted striping.

Change-Id: Id8156876a90b4caf9d687637e14c7ad4a66ceda6
Signed-off-by: default avatarBen Walker <benjamin.walker@intel.com>
parent 2bd8c87a

lib/nvme/nvme_ctrlr.c

+1 −12
Original line number Diff line number Diff line
@@ -225,17 +225,11 @@ static void 
nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,

		struct spdk_nvme_intel_log_page_directory *log_page_directory)

{

	struct spdk_pci_id pci_id;



	if (log_page_directory == NULL) {

		return;

	}



	if (nvme_transport_ctrlr_get_pci_id(ctrlr, &pci_id)) {

		return;

	}



	if (pci_id.vendor_id != SPDK_PCI_VID_INTEL) {

	if (ctrlr->cdata.vid != SPDK_PCI_VID_INTEL) {

		return;

	}
@@ -1286,7 +1280,6 @@ nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx) 
int

nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)

{

	struct spdk_pci_id pci_id;

	int rc;



	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
@@ -1305,10 +1298,6 @@ nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr) 
		return rc;

	}



	if (nvme_transport_ctrlr_get_pci_id(ctrlr, &pci_id) == 0) {

		ctrlr->quirks = nvme_get_quirks(&pci_id);

	}



	TAILQ_INIT(&ctrlr->active_procs);



	return rc;

lib/nvme/nvme_internal.h

+6 −2
Original line number Diff line number Diff line
@@ -78,6 +78,12 @@ 
 */

#define NVME_QUIRK_DELAY_BEFORE_CHK_RDY	0x4



/*

 * The controller performs best when I/O is split on particular

 * LBA boundaries.

 */

#define NVME_INTEL_QUIRK_STRIPING 0x8



#define NVME_MAX_ASYNC_EVENTS	(8)



#define NVME_MIN_TIMEOUT_PERIOD		(5)
@@ -419,8 +425,6 @@ extern struct nvme_driver *g_spdk_nvme_driver; 


#define nvme_min(a,b) (((a)<(b))?(a):(b))



#define INTEL_DC_P3X00_DEVID	0x0953



#define nvme_delay		usleep



static inline uint32_t

lib/nvme/nvme_ns.c

+3 −8
Original line number Diff line number Diff line
@@ -183,21 +183,16 @@ spdk_nvme_ns_get_data(struct spdk_nvme_ns *ns) 
int nvme_ns_construct(struct spdk_nvme_ns *ns, uint16_t id,

		      struct spdk_nvme_ctrlr *ctrlr)

{

	struct spdk_pci_id pci_id;



	assert(id > 0);



	ns->ctrlr = ctrlr;

	ns->id = id;

	ns->stripe_size = 0;



	if (nvme_transport_ctrlr_get_pci_id(ctrlr, &pci_id) == 0) {

		if (pci_id.vendor_id == SPDK_PCI_VID_INTEL &&

		    pci_id.device_id == INTEL_DC_P3X00_DEVID &&

	if (ctrlr->quirks & NVME_INTEL_QUIRK_STRIPING &&

	    ctrlr->cdata.vs[3] != 0) {

		ns->stripe_size = (1 << ctrlr->cdata.vs[3]) * ctrlr->min_page_size;

	}

	}



	return nvme_ns_identify_update(ns);

}

lib/nvme/nvme_pcie.c

+2 −0
Original line number Diff line number Diff line
@@ -632,6 +632,8 @@ struct spdk_nvme_ctrlr *nvme_pcie_ctrlr_construct(enum spdk_nvme_transport_type 
		return NULL;

	}



	pctrlr->ctrlr.quirks = nvme_get_quirks(&probe_info->pci_id);



	rc = nvme_pcie_ctrlr_construct_admin_qpair(&pctrlr->ctrlr);

	if (rc != 0) {

		nvme_ctrlr_destruct(&pctrlr->ctrlr);

lib/nvme/nvme_quirks.c

+9 −8
Original line number Diff line number Diff line
@@ -39,12 +39,13 @@ struct nvme_quirk { 
};



static const struct nvme_quirk nvme_quirks[] = {

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3702}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_STRIPING	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3703}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_STRIPING	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3704}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_STRIPING	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3705}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_STRIPING	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x3709}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_STRIPING	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_VID_INTEL, 0x370a}, NVME_INTEL_QUIRK_READ_LATENCY | NVME_INTEL_QUIRK_WRITE_LATENCY | NVME_INTEL_QUIRK_STRIPING	},

	{{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID}, NVME_INTEL_QUIRK_STRIPING								},

	{{SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID}, NVME_QUIRK_DELAY_BEFORE_CHK_RDY							},

	{{0x0000, 0x0000, 0x0000, 0x0000}, 0															}

};