Commit 7ff9609f authored by Jim Harris's avatar Jim Harris Committed by Tomasz Zawadzki
Browse files

nvme: add security send/receive quirk for Intel 900P SSDs 



These SSDs set the oacs.security bit but do not actually
support OPAL.  So do not set the controller flag indicating
SECURITY_SEND_RECV support in this case.

Signed-off-by: default avatarJim Harris <james.r.harris@intel.com>
Change-Id: I7fcfeafcc8d9439a1c53c60a1aea1801923a2ce5

Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/3156


Community-CI: Broadcom CI
Community-CI: Mellanox Build Bot
Reviewed-by: default avatarChangpeng Liu <changpeng.liu@intel.com>
Reviewed-by: default avatarBen Walker <benjamin.walker@intel.com>
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
parent cd8b9455

lib/nvme/nvme_ctrlr.c

+1 −1
Original line number Diff line number Diff line
@@ -1355,7 +1355,7 @@ nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl) 
		SPDK_DEBUGLOG(SPDK_LOG_NVME, "transport max_sges %u\n", ctrlr->max_sges);

	}



	if (ctrlr->cdata.oacs.security) {

	if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {

		ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;

	}

lib/nvme/nvme_internal.h

+5 −0
Original line number Diff line number Diff line
@@ -145,6 +145,11 @@ extern pid_t g_spdk_nvme_pid; 
 */

#define NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH 0x1000



/**

 * The SSD does not support OPAL even through it sets the security bit in OACS.

 */

#define NVME_QUIRK_OACS_SECURITY 0x2000



#define NVME_MAX_ASYNC_EVENTS	(8)



#define NVME_MAX_ADMIN_TIMEOUT_IN_SECS	(30)

lib/nvme/nvme_quirks.c

+3 −0
Original line number Diff line number Diff line
@@ -93,6 +93,9 @@ static const struct nvme_quirk nvme_quirks[] = { 
	{	{SPDK_PCI_VID_VMWARE, 0x07f0, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},

		NVME_QUIRK_SHST_COMPLETE

	},

	{	{SPDK_PCI_VID_INTEL, 0x2700, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},

		NVME_QUIRK_OACS_SECURITY

	},

	{	{0x0000, 0x0000, 0x0000, 0x0000}, 0}

};