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external_code/nvme: enable PCIe bus master and disable INTx irqs
It allows the controller to issue memory read/writes (the bus master enable bit) and disables the ability to generate INTx interrupts which won't be serviced. Signed-off-by:Konrad Sztyber <konrad.sztyber@intel.com> Change-Id: I3b041f1ea7c2bc275b609afcc3d1e4f655aee4c5 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6669 Tested-by:
SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by:
Tomasz Zawadzki <tomasz.zawadzki@intel.com> Reviewed-by:
Jim Harris <james.r.harris@intel.com> Reviewed-by:
Ben Walker <benjamin.walker@intel.com>