Commit 76fae149 authored by paul luse's avatar paul luse Committed by Tomasz Zawadzki
Browse files

lib/idxd: update names from IDXD->DSA where it makes sense 



In prep for upcoming addition of IAA.

Signed-off-by: default avatarpaul luse <paul.e.luse@intel.com>
Change-Id: I47c5880aac37da9a38d6af6e52a51cefbfec91b9
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/12762


Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarBen Walker <benjamin.walker@intel.com>
Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
Community-CI: Mellanox Build Bot
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
parent 46ac1b8d

doc/idxd.md

+6 −5
Original line number Diff line number Diff line
@@ -15,10 +15,11 @@ spdk_idxd_submit_crc32c() | @copybrief spdk_idxd_submit_crc32c() 
spdk_idxd_submit_dualcast               | @copybrief spdk_idxd_submit_dualcast()

spdk_idxd_submit_fill()                 | @copybrief spdk_idxd_submit_fill()



## Pre-defined configurations {#idxd_configs}

## Pre-defined configuration {#idxd_configs}



The RPC `idxd_scan_accel_engine` is used to both enable IDXD and set it's

configuration to one of two pre-defined configs:

The low level library can be initialized either directly via `spdk_idxd_set_config` or

through an RPC via one of the accelerator framework modules that rely on the low level

IDXD library.  Either way, the underlying hardware will be set to the pre-defined

hardware configuration below:



Config #0: 4 groups, 1 work queue per group, 1 engine per group.

Config #1: 2 groups, 2 work queues per group, 2 engines per group.
 
Config: 1 group, 1 work queue, 4 engines in the group.

include/spdk/idxd_spec.h

+32 −33
Original line number Diff line number Diff line
@@ -66,39 +66,38 @@ extern "C" { 
#define IDXD_FLAG_CRC_READ_CRC_SEED	(1 << 16)



/*

 * IDXD is a family of devices, DSA is the only currently

 * supported one.

 * IDXD is a family of devices, DSA and IAA.

 */

enum dsa_completion_status {

	IDXD_COMP_NONE			= 0,

	IDXD_COMP_SUCCESS		= 1,

	IDXD_COMP_SUCCESS_PRED		= 2,

	IDXD_COMP_PAGE_FAULT_NOBOF	= 3,

	IDXD_COMP_PAGE_FAULT_IR		= 4,

	IDXD_COMP_BATCH_FAIL		= 5,

	IDXD_COMP_BATCH_PAGE_FAULT	= 6,

	IDXD_COMP_DR_OFFSET_NOINC	= 7,

	IDXD_COMP_DR_OFFSET_ERANGE	= 8,

	IDXD_COMP_DIF_ERR		= 9,

	IDXD_COMP_BAD_OPCODE		= 16,

	IDXD_COMP_INVALID_FLAGS		= 17,

	IDXD_COMP_NOZERO_RESERVE	= 18,

	IDXD_COMP_XFER_ERANGE		= 19,

	IDXD_COMP_DESC_CNT_ERANGE	= 20,

	IDXD_COMP_DR_ERANGE		= 21,

	IDXD_COMP_OVERLAP_BUFFERS	= 22,

	IDXD_COMP_DCAST_ERR		= 23,

	IDXD_COMP_DESCLIST_ALIGN	= 24,

	IDXD_COMP_INT_HANDLE_INVAL	= 25,

	IDXD_COMP_CRA_XLAT		= 26,

	IDXD_COMP_CRA_ALIGN		= 27,

	IDXD_COMP_ADDR_ALIGN		= 28,

	IDXD_COMP_PRIV_BAD		= 29,

	IDXD_COMP_TRAFFIC_CLASS_CONF	= 30,

	IDXD_COMP_PFAULT_RDBA		= 31,

	IDXD_COMP_HW_ERR1		= 32,

	IDXD_COMP_HW_ERR_DRB		= 33,

	IDXD_COMP_TRANSLATION_FAIL	= 34,

	DSA_COMP_NONE			= 0,

	DSA_COMP_SUCCESS		= 1,

	DSA_COMP_SUCCESS_PRED		= 2,

	DSA_COMP_PAGE_FAULT_NOBOF	= 3,

	DSA_COMP_PAGE_FAULT_IR		= 4,

	DSA_COMP_BATCH_FAIL		= 5,

	DSA_COMP_BATCH_PAGE_FAULT	= 6,

	DSA_COMP_DR_OFFSET_NOINC	= 7,

	DSA_COMP_DR_OFFSET_ERANGE	= 8,

	DSA_COMP_DIF_ERR		= 9,

	DSA_COMP_BAD_OPCODE		= 16,

	DSA_COMP_INVALID_FLAGS		= 17,

	DSA_COMP_NOZERO_RESERVE		= 18,

	DSA_COMP_XFER_ERANGE		= 19,

	DSA_COMP_DESC_CNT_ERANGE	= 20,

	DSA_COMP_DR_ERANGE		= 21,

	DSA_COMP_OVERLAP_BUFFERS	= 22,

	DSA_COMP_DCAST_ERR		= 23,

	DSA_COMP_DESCLIST_ALIGN		= 24,

	DSA_COMP_INT_HANDLE_INVAL	= 25,

	DSA_COMP_CRA_XLAT		= 26,

	DSA_COMP_CRA_ALIGN		= 27,

	DSA_COMP_ADDR_ALIGN		= 28,

	DSA_COMP_PRIV_BAD		= 29,

	DSA_COMP_TRAFFIC_CLASS_CONF	= 30,

	DSA_COMP_PFAULT_RDBA		= 31,

	DSA_COMP_HW_ERR1		= 32,

	DSA_COMP_HW_ERR_DRB		= 33,

	DSA_COMP_TRANSLATION_FAIL	= 34,

};



enum idxd_wq_state {
@@ -253,7 +252,7 @@ struct idxd_hw_desc { 
} __attribute((aligned(64)));

SPDK_STATIC_ASSERT(sizeof(struct idxd_hw_desc) == 64, "size mismatch");



struct idxd_hw_comp_record {

struct dsa_hw_comp_record {

	volatile uint8_t	status;

	union {

		uint8_t		result;
@@ -287,7 +286,7 @@ struct idxd_hw_comp_record { 
		uint8_t		op_specific[16];

	};

};

SPDK_STATIC_ASSERT(sizeof(struct idxd_hw_comp_record) == 32, "size mismatch");

SPDK_STATIC_ASSERT(sizeof(struct dsa_hw_comp_record) == 32, "size mismatch");



union idxd_gencap_register {

	struct {

lib/idxd/idxd.c

+2 −2
Original line number Diff line number Diff line
@@ -199,7 +199,7 @@ spdk_idxd_get_channel(struct spdk_idxd_device *idxd) 
	for (i = 0; i < num_descriptors; i++) {

		STAILQ_INSERT_TAIL(&chan->ops_pool, op, link);

		op->desc = desc;

		rc = _vtophys(&op->hw, &desc->completion_addr, sizeof(struct idxd_hw_comp_record));

		rc = _vtophys(&op->hw, &desc->completion_addr, sizeof(struct dsa_hw_comp_record));

		if (rc) {

			SPDK_ERRLOG("Failed to translate completion memory\n");

			goto err_op;
@@ -241,7 +241,7 @@ spdk_idxd_get_channel(struct spdk_idxd_device *idxd) 
		}



		for (j = 0; j < DESC_PER_BATCH; j++) {

			rc = _vtophys(&op->hw, &desc->completion_addr, sizeof(struct idxd_hw_comp_record));

			rc = _vtophys(&op->hw, &desc->completion_addr, sizeof(struct dsa_hw_comp_record));

			if (rc) {

				SPDK_ERRLOG("Failed to translate batch entry completion memory\n");

				goto err_user_desc_or_op;

lib/idxd/idxd.h

+1 −1
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ struct pci_dev_id { 
 * size and must be 32 byte aligned.

 */

struct idxd_ops {

	struct idxd_hw_comp_record	hw;

	struct dsa_hw_comp_record	hw;

	void				*cb_arg;

	spdk_idxd_req_cb		cb_fn;

	struct idxd_batch		*batch;