Commit 75440d05 authored by Michael Bang's avatar Michael Bang Committed by Tomasz Zawadzki
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doc: correct explanation of NVMe SQ command submission 



Correct explanation of NVMe SQ command submission

Change-Id: Ibdb3d13369c916708269c18fc04d5680044fce8e
Signed-off-by: default avatarMichael Bang <mi.bang@samsung.com>
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/6027


Community-CI: Mellanox Build Bot
Reviewed-by: default avatarChangpeng Liu <changpeng.liu@intel.com>
Reviewed-by: default avatarsunshihao <sunshihao@huawei.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarAleksey Marchuk <alexeymar@mellanox.com>
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
parent 43c20701

doc/nvme_spec.md

+2 −2
Original line number Diff line number Diff line
@@ -20,8 +20,8 @@ registers involved that are called doorbells. 


An I/O is submitted to an NVMe device by constructing a 64 byte command, placing

it into the submission queue at the current location of the submission queue

head index, and then writing the new index of the submission queue head to the

submission queue head doorbell register. It's actually valid to copy a whole set

tail index, and then writing the new index of the submission queue tail to the

submission queue tail doorbell register. It's actually valid to copy a whole set

of commands into open slots in the ring and then write the doorbell just one

time to submit the whole batch.