Commit 686a24ed authored by Alexey Marchuk's avatar Alexey Marchuk Committed by Konrad Sztyber
Browse files

accel/mlx5: Factor our UMR config into function 



In this way we first configure N UMRs and then do
N RDMA operations, this approach allows more HW
optimiztions in future

Signed-off-by: default avatarAlexey Marchuk <alexeymar@nvidia.com>
Change-Id: Iefd823a1458af518b9a2d098ed5a0fb777d6e93f
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23112


Reviewed-by: default avatarBen Walker <ben@nvidia.com>
Community-CI: Mellanox Build Bot
Reviewed-by: default avatarShuhei Matsumoto <smatsumoto@nvidia.com>
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
parent cbd4659b

module/accel/mlx5/accel_mlx5.c

+69 −45
Original line number Diff line number Diff line
@@ -405,58 +405,43 @@ accel_mlx5_task_alloc_mkeys(struct accel_mlx5_task *task) 
}



static inline int

accel_mlx5_task_process(struct accel_mlx5_task *mlx5_task)

accel_mlx5_configure_crypto_umr(struct accel_mlx5_task *mlx5_task, struct accel_mlx5_sge *sge,

				struct mlx5dv_mkey *mkey, uint32_t num_blocks, uint64_t iv)

{

	struct accel_mlx5_sge sges[ACCEL_MLX5_MAX_MKEYS_IN_TASK];

	struct spdk_accel_task *task = &mlx5_task->base;

	struct mlx5dv_crypto_attr cattr;

	struct accel_mlx5_dev *dev = mlx5_task->dev;

	struct accel_mlx5_qp *qp = dev->qp;

	struct ibv_qp_ex *qpx = qp->qpex;

	struct mlx5dv_qp_ex *mqpx = qp->mqpx;

	struct spdk_accel_task *task = &mlx5_task->base;

	struct mlx5dv_mkey_conf_attr mkey_attr = {};

	struct mlx5dv_crypto_attr cattr;

	uint64_t iv;

	uint32_t num_setters = 3, i; /* access flags, layout, crypto */

	uint32_t length;

	uint32_t num_setters = 3; /* access flags, layout, crypto */

	int rc;

	uint32_t num_ops = spdk_min(mlx5_task->num_reqs - mlx5_task->num_completed_reqs,

				    mlx5_task->num_ops);



	if (spdk_unlikely(!num_ops)) {

		return -EINVAL;

	}



	iv = task->iv + mlx5_task->num_completed_reqs;



	if (!qp->wr_started) {

		ibv_wr_start(qpx);

		qp->wr_started = true;

	}



	SPDK_DEBUGLOG(accel_mlx5, "begin, task, %p, reqs: total %u, submitted %u, completed %u\n",

		      mlx5_task, mlx5_task->num_reqs, mlx5_task->num_submitted_reqs, mlx5_task->num_completed_reqs);



	for (i = 0; i < num_ops; i++) {

		rc = accel_mlx5_fill_block_sge(dev, sges[i].src_sge, &mlx5_task->src, task->block_size,

					       task->src_domain, task->src_domain_ctx);

	length = num_blocks * task->block_size;

	SPDK_DEBUGLOG(accel_mlx5, "task %p, src KLM, domain %p, len %u\n", task, task->src_domain, length);

	rc = accel_mlx5_fill_block_sge(dev, sge->src_sge, &mlx5_task->src, length, task->src_domain,

				       task->src_domain_ctx);

	if (spdk_unlikely(rc <= 0)) {

		if (rc == 0) {

			rc = -EINVAL;

		}

		SPDK_ERRLOG("failed set src sge, rc %d\n", rc);

			goto err_out;

		return rc;

	}

		sges[i].src_sge_count = rc;

	sge->src_sge_count = rc;



	/* prepare memory key - destination for WRITE operation */

	qpx->wr_flags = IBV_SEND_INLINE;

	qpx->wr_id = (uint64_t)(void *)mlx5_task;

		mlx5dv_wr_mkey_configure(mqpx, mlx5_task->mkeys[i]->mkey, num_setters, &mkey_attr);

	mlx5dv_wr_mkey_configure(mqpx, mkey, num_setters, &mkey_attr);

	mlx5dv_wr_set_mkey_access_flags(mqpx,

					IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE | IBV_ACCESS_REMOTE_READ);

	if (mlx5_task->inplace) {

			mlx5dv_wr_set_mkey_layout_list(mqpx, sges[i].src_sge_count, sges[i].src_sge);

		mlx5dv_wr_set_mkey_layout_list(mqpx, sge->src_sge_count, sge->src_sge);

	} else {

			rc = accel_mlx5_fill_block_sge(dev, sges[i].dst_sge, &mlx5_task->dst, task->block_size,

		rc = accel_mlx5_fill_block_sge(dev, sge->dst_sge, &mlx5_task->dst, length,

					       task->dst_domain, task->dst_domain_ctx);

		if (spdk_unlikely(rc <= 0)) {

			if (rc == 0) {
@@ -464,10 +449,10 @@ accel_mlx5_task_process(struct accel_mlx5_task *mlx5_task) 
			}

			SPDK_ERRLOG("failed set dst sge, rc %d\n", rc);

			mlx5_task->rc = rc;

				goto err_out;

			return rc;

		}

			sges[i].dst_sge_count = rc;

			mlx5dv_wr_set_mkey_layout_list(mqpx, sges[i].dst_sge_count, sges[i].dst_sge);

		sge->dst_sge_count = rc;

		mlx5dv_wr_set_mkey_layout_list(mqpx, sge->dst_sge_count, sge->dst_sge);

	}

	SPDK_DEBUGLOG(accel_mlx5, "task %p crypto_attr: bs %u, iv %"PRIu64", enc_on_tx %d\n", task,

		      task->block_size, iv, mlx5_task->encrypt_on_tx);
@@ -476,10 +461,49 @@ accel_mlx5_task_process(struct accel_mlx5_task *mlx5_task) 
	if (spdk_unlikely(rc)) {

		SPDK_ERRLOG("failed to set crypto attr, rc %d\n", rc);

		mlx5_task->rc = rc;

			goto err_out;

		return rc;

	}

	mlx5dv_wr_set_mkey_crypto(mqpx, &cattr);



	return 0;

}



static inline int

accel_mlx5_task_process(struct accel_mlx5_task *mlx5_task)

{

	struct accel_mlx5_sge sges[ACCEL_MLX5_MAX_MKEYS_IN_TASK];

	struct spdk_accel_task *task = &mlx5_task->base;

	struct accel_mlx5_dev *dev = mlx5_task->dev;

	struct accel_mlx5_qp *qp = dev->qp;

	struct ibv_qp_ex *qpx = qp->qpex;

	uint64_t iv;

	uint32_t i;

	int rc;

	uint32_t num_ops = spdk_min(mlx5_task->num_reqs - mlx5_task->num_completed_reqs,

				    mlx5_task->num_ops);



	if (spdk_unlikely(!num_ops)) {

		return -EINVAL;

	}



	iv = task->iv + mlx5_task->num_completed_reqs;



	if (!qp->wr_started) {

		ibv_wr_start(qpx);

		qp->wr_started = true;

	}



	SPDK_DEBUGLOG(accel_mlx5, "begin, task, %p, reqs: total %u, submitted %u, completed %u\n",

		      mlx5_task, mlx5_task->num_reqs, mlx5_task->num_submitted_reqs, mlx5_task->num_completed_reqs);

	for (i = 0; i < num_ops; i++) {

		rc = accel_mlx5_configure_crypto_umr(mlx5_task, &sges[i], mlx5_task->mkeys[i]->mkey, 1, iv++);

		if (spdk_unlikely(rc)) {

			SPDK_ERRLOG("UMR configure failed with %d\n", rc);

			goto err_out;

		}

	}



	for (i = 0; i < num_ops; i++) {

		/* Prepare WRITE, use rkey from mkey, remote addr is always 0 - start of the mkey */

		qpx->wr_flags = IBV_SEND_SIGNALED;

		qpx->wr_id = (uint64_t)(void *)mlx5_task;