Commit 4bce7047 authored by Konrad Sztyber's avatar Konrad Sztyber Committed by Jim Harris
Browse files

lib/vmd: separate base / limit registers reset function 



Moved the base / limit register reset to a separate function.  It'll
make it easier to perform the reset only under specific conditions are
met (e.g. only during the initial setup).

Change-Id: I5231e6d5a1e1673885bf549b1b6761092b4b62be
Signed-off-by: default avatarKonrad Sztyber <konrad.sztyber@intel.com>
Reviewed-on: https://review.gerrithub.io/c/spdk/spdk/+/472248


Reviewed-by: default avatarWojciech Malikowski <wojciech.malikowski@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarTomasz Zawadzki <tomasz.zawadzki@intel.com>
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
parent 7135856e

lib/vmd/vmd.c

+37 −29
Original line number Diff line number Diff line
@@ -329,6 +329,42 @@ vmd_read_config_space(struct vmd_pci_device *dev) 
			DEVICE_SERIAL_NUMBER_CAP_ID);

}



static void

vmd_reset_base_limit_registers(struct vmd_pci_device *dev)

{

	uint32_t reg __attribute__((unused));



	assert(dev->header_type != PCI_HEADER_TYPE_NORMAL);

	/*

	 * Writes to the pci config space are posted writes.

	 * To ensure transaction reaches its destination

	 * before another write is posted, an immediate read

	 * of the written value should be performed.

	 */

	dev->header->one.mem_base = 0xfff0;

	reg = dev->header->one.mem_base;

	dev->header->one.mem_limit = 0x0;

	reg = dev->header->one.mem_limit;

	dev->header->one.prefetch_base = 0x0;

	reg = dev->header->one.prefetch_base;

	dev->header->one.prefetch_limit = 0x0;

	reg = dev->header->one.prefetch_limit;

	dev->header->one.prefetch_base_upper = 0x0;

	reg = dev->header->one.prefetch_base_upper;

	dev->header->one.prefetch_limit_upper = 0x0;

	reg = dev->header->one.prefetch_limit_upper;

	dev->header->one.io_base_upper = 0x0;

	reg = dev->header->one.io_base_upper;

	dev->header->one.io_limit_upper = 0x0;

	reg = dev->header->one.io_limit_upper;

	dev->header->one.primary = 0;

	reg = dev->header->one.primary;

	dev->header->one.secondary = 0;

	reg = dev->header->one.secondary;

	dev->header->one.subordinate = 0;

	reg = dev->header->one.subordinate;

}



static struct vmd_pci_device *

vmd_alloc_dev(struct vmd_pci_bus *bus, uint32_t devfn)

{
@@ -336,7 +372,6 @@ vmd_alloc_dev(struct vmd_pci_bus *bus, uint32_t devfn) 
	struct pci_header volatile *header;

	uint8_t header_type;

	uint32_t rev_class;

	uint32_t reg __attribute__((unused));



	header = (struct pci_header * volatile)(bus->vmd->cfg_vaddr +

						CONFIG_OFFSET_ADDR(bus->bus_number, devfn, 0, 0));
@@ -368,34 +403,7 @@ vmd_alloc_dev(struct vmd_pci_bus *bus, uint32_t devfn) 
	dev->header_type = header_type & 0x7;



	if (header_type == PCI_HEADER_TYPE_BRIDGE) {

		dev->header->one.mem_base = 0xfff0;

		/*

		 * Writes to the pci config space are posted writes.

		 * To ensure transaction reaches its destination

		 * before another write is posted, an immediate read

		 * of the written value should be performed.

		 */

		reg = dev->header->one.mem_base;

		dev->header->one.mem_limit = 0x0;

		reg = dev->header->one.mem_limit;

		dev->header->one.prefetch_base = 0x0;

		reg = dev->header->one.prefetch_base;

		dev->header->one.prefetch_limit = 0x0;

		reg = dev->header->one.prefetch_limit;

		dev->header->one.prefetch_base_upper = 0x0;

		reg = dev->header->one.prefetch_base_upper;

		dev->header->one.prefetch_limit_upper = 0x0;

		reg = dev->header->one.prefetch_limit_upper;

		dev->header->one.io_base_upper = 0x0;

		reg = dev->header->one.io_base_upper;

		dev->header->one.io_limit_upper = 0x0;

		reg = dev->header->one.io_limit_upper;

		dev->header->one.primary = 0;

		reg = dev->header->one.primary;

		dev->header->one.secondary = 0;

		reg = dev->header->one.secondary;

		dev->header->one.subordinate = 0;

		reg = dev->header->one.subordinate;

		vmd_reset_base_limit_registers(dev);

	}



	vmd_read_config_space(dev);