Commit 43824348 authored by PepperJo's avatar PepperJo Committed by Jim Harris
Browse files

nvme/pcie: add memory barrier process completions 



Because ppc64 has less strict memory ordering behaviour
than x86 we need to introduce a memory barrier when
polling for completions due to possible reordering
of tracker and cpl access.

Change-Id: Id17116c38b2ba69154c175c539fc97c60897deb0
Signed-off-by: default avatarJonas Pfefferle <jpf@zurich.ibm.com>
Reviewed-on: https://review.gerrithub.io/383728


Tested-by: default avatarSPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarDaniel Verkamp <daniel.verkamp@intel.com>
parent 7bcb08c0

lib/nvme/nvme_pcie.c

+8 −0
Original line number Diff line number Diff line
@@ -1907,6 +1907,14 @@ nvme_pcie_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_ 


		if (cpl->status.p != pqpair->phase)

			break;

#ifdef __PPC64__

		/*

		 * This memory barrier prevents reordering of:

		 * - load after store from/to tr

		 * - load after load cpl phase and cpl cid

		 */

		spdk_mb();

#endif



		tr = &pqpair->tr[cpl->cid];