Loading include/spdk/ioat.h +1 −0 Original line number Diff line number Diff line Loading @@ -40,6 +40,7 @@ #include <inttypes.h> #include <stdbool.h> #include "spdk/pci.h" /** * Signature for callback function invoked when a request is completed. Loading include/spdk/nvme.h +1 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ #define SPDK_NVME_H #include <stddef.h> #include "spdk/pci.h" #include "nvme_spec.h" /** \file Loading include/spdk/pci.h +12 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ #define SPDK_PCI_H #ifdef USE_PCIACCESS #include <pciaccess.h> #define spdk_pci_device_get_domain(dev) (dev->domain) #define spdk_pci_device_get_bus(dev) (dev->bus) #define spdk_pci_device_get_dev(pdev) (pdev->dev) Loading @@ -43,6 +44,17 @@ #define spdk_pci_device_get_device_id(dev) (dev->device_id) #define spdk_pci_device_get_subvendor_id(dev) (dev->subvendor_id) #define spdk_pci_device_get_subdevice_id(dev) (dev->subdevice_id) #else #include <rte_pci.h> typedef struct rte_pci_device spdk_pci_device; typedef struct rte_pci_driver spdk_pci_driver; #define spdk_pci_device_get_domain(dev) (dev->addr.domain) #define spdk_pci_device_get_bus(dev) (dev->addr.bus) #define spdk_pci_device_get_dev(dev) (dev->addr.devid) #define spdk_pci_device_get_func(dev) (dev->addr.function) #endif #define PCI_CFG_SIZE 256 Loading lib/ioat/ioat_impl.h +88 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,6 @@ #include <assert.h> #include <pthread.h> #include <pciaccess.h> #include <stdio.h> #include <rte_malloc.h> #include <rte_config.h> Loading @@ -11,6 +10,10 @@ #include <rte_cycles.h> #include "spdk/vtophys.h" #include "spdk/pci.h" #include "spdk/ioat.h" #include "ioat_pci.h" /** * \file Loading Loading @@ -84,6 +87,90 @@ ioat_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr) return pci_device_unmap_range(dev, addr, dev->regions[bar].size); } #else /* var should be the pointer */ #define ioat_pcicfg_read32(handle, var, offset) rte_eal_pci_read_config(handle, var, 4, offset) #define ioat_pcicfg_write32(handle, var, offset) rte_eal_pci_write_config(handle, var, 4, offset) static inline int ioat_pcicfg_map_bar(void *devhandle, uint32_t bar, uint32_t read_only, void **mapped_addr) { struct rte_pci_device *dev = devhandle; *mapped_addr = dev->mem_resource[bar].addr; return 0; } static struct rte_pci_id ioat_driver_id[] = { {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9)}, { .vendor_id = 0, /* sentinel */ }, }; static struct rte_pci_driver ioat_rte_driver = { .name = "ioat_driver", .devinit = NULL, .id_table = ioat_driver_id, .drv_flags = RTE_PCI_DRV_NEED_MAPPING, }; static inline int ioat_driver_register_dev_init(void *fn_t) { int rc; ioat_rte_driver.devinit = fn_t; rte_eal_pci_register(&ioat_rte_driver); rc = rte_eal_pci_probe(); rte_eal_pci_unregister(&ioat_rte_driver); return rc; } #endif typedef pthread_mutex_t ioat_mutex_t; Loading lib/nvme/nvme_impl.h +48 −2 Original line number Diff line number Diff line Loading @@ -35,8 +35,9 @@ #define __NVME_IMPL_H__ #include "spdk/vtophys.h" #include "spdk/pci.h" #include "spdk/nvme_spec.h" #include <assert.h> #include <pciaccess.h> #include <rte_malloc.h> #include <rte_config.h> #include <rte_mempool.h> Loading Loading @@ -172,7 +173,52 @@ nvme_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr) return pci_device_unmap_range(dev, addr, dev->regions[bar].size); } #endif #else /* var should be the pointer */ #define nvme_pcicfg_read32(handle, var, offset) rte_eal_pci_read_config(handle, var, 4, offset) #define nvme_pcicfg_write32(handle, var, offset) rte_eal_pci_write_config(handle, var, 4, offset) static inline int nvme_pcicfg_map_bar(void *devhandle, uint32_t bar, uint32_t read_only, void **mapped_addr) { struct rte_pci_device *dev = devhandle; *mapped_addr = dev->mem_resource[bar].addr; return 0; } static inline int nvme_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr) { return 0; } static struct rte_pci_id nvme_pci_driver_id[] = { {RTE_PCI_DEVICE(0x8086, 0x0953)}, { .vendor_id = 0, /* sentinel */ }, }; static struct rte_pci_driver nvme_rte_driver = { .name = "nvme_driver", .devinit = NULL, .id_table = nvme_pci_driver_id, .drv_flags = RTE_PCI_DRV_NEED_MAPPING, }; static inline int nvme_driver_register_dev_init(pci_driver_init fn_t) { int rc; nvme_rte_driver.devinit = fn_t; rte_eal_pci_register(&nvme_rte_driver); rc = rte_eal_pci_probe(); rte_eal_pci_unregister(&nvme_rte_driver); return rc; } #endif /* !USE_PCIACCESS */ typedef pthread_mutex_t nvme_mutex_t; Loading Loading
include/spdk/ioat.h +1 −0 Original line number Diff line number Diff line Loading @@ -40,6 +40,7 @@ #include <inttypes.h> #include <stdbool.h> #include "spdk/pci.h" /** * Signature for callback function invoked when a request is completed. Loading
include/spdk/nvme.h +1 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ #define SPDK_NVME_H #include <stddef.h> #include "spdk/pci.h" #include "nvme_spec.h" /** \file Loading
include/spdk/pci.h +12 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ #define SPDK_PCI_H #ifdef USE_PCIACCESS #include <pciaccess.h> #define spdk_pci_device_get_domain(dev) (dev->domain) #define spdk_pci_device_get_bus(dev) (dev->bus) #define spdk_pci_device_get_dev(pdev) (pdev->dev) Loading @@ -43,6 +44,17 @@ #define spdk_pci_device_get_device_id(dev) (dev->device_id) #define spdk_pci_device_get_subvendor_id(dev) (dev->subvendor_id) #define spdk_pci_device_get_subdevice_id(dev) (dev->subdevice_id) #else #include <rte_pci.h> typedef struct rte_pci_device spdk_pci_device; typedef struct rte_pci_driver spdk_pci_driver; #define spdk_pci_device_get_domain(dev) (dev->addr.domain) #define spdk_pci_device_get_bus(dev) (dev->addr.bus) #define spdk_pci_device_get_dev(dev) (dev->addr.devid) #define spdk_pci_device_get_func(dev) (dev->addr.function) #endif #define PCI_CFG_SIZE 256 Loading
lib/ioat/ioat_impl.h +88 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,6 @@ #include <assert.h> #include <pthread.h> #include <pciaccess.h> #include <stdio.h> #include <rte_malloc.h> #include <rte_config.h> Loading @@ -11,6 +10,10 @@ #include <rte_cycles.h> #include "spdk/vtophys.h" #include "spdk/pci.h" #include "spdk/ioat.h" #include "ioat_pci.h" /** * \file Loading Loading @@ -84,6 +87,90 @@ ioat_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr) return pci_device_unmap_range(dev, addr, dev->regions[bar].size); } #else /* var should be the pointer */ #define ioat_pcicfg_read32(handle, var, offset) rte_eal_pci_read_config(handle, var, 4, offset) #define ioat_pcicfg_write32(handle, var, offset) rte_eal_pci_write_config(handle, var, 4, offset) static inline int ioat_pcicfg_map_bar(void *devhandle, uint32_t bar, uint32_t read_only, void **mapped_addr) { struct rte_pci_device *dev = devhandle; *mapped_addr = dev->mem_resource[bar].addr; return 0; } static struct rte_pci_id ioat_driver_id[] = { {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8)}, {RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9)}, { .vendor_id = 0, /* sentinel */ }, }; static struct rte_pci_driver ioat_rte_driver = { .name = "ioat_driver", .devinit = NULL, .id_table = ioat_driver_id, .drv_flags = RTE_PCI_DRV_NEED_MAPPING, }; static inline int ioat_driver_register_dev_init(void *fn_t) { int rc; ioat_rte_driver.devinit = fn_t; rte_eal_pci_register(&ioat_rte_driver); rc = rte_eal_pci_probe(); rte_eal_pci_unregister(&ioat_rte_driver); return rc; } #endif typedef pthread_mutex_t ioat_mutex_t; Loading
lib/nvme/nvme_impl.h +48 −2 Original line number Diff line number Diff line Loading @@ -35,8 +35,9 @@ #define __NVME_IMPL_H__ #include "spdk/vtophys.h" #include "spdk/pci.h" #include "spdk/nvme_spec.h" #include <assert.h> #include <pciaccess.h> #include <rte_malloc.h> #include <rte_config.h> #include <rte_mempool.h> Loading Loading @@ -172,7 +173,52 @@ nvme_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr) return pci_device_unmap_range(dev, addr, dev->regions[bar].size); } #endif #else /* var should be the pointer */ #define nvme_pcicfg_read32(handle, var, offset) rte_eal_pci_read_config(handle, var, 4, offset) #define nvme_pcicfg_write32(handle, var, offset) rte_eal_pci_write_config(handle, var, 4, offset) static inline int nvme_pcicfg_map_bar(void *devhandle, uint32_t bar, uint32_t read_only, void **mapped_addr) { struct rte_pci_device *dev = devhandle; *mapped_addr = dev->mem_resource[bar].addr; return 0; } static inline int nvme_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr) { return 0; } static struct rte_pci_id nvme_pci_driver_id[] = { {RTE_PCI_DEVICE(0x8086, 0x0953)}, { .vendor_id = 0, /* sentinel */ }, }; static struct rte_pci_driver nvme_rte_driver = { .name = "nvme_driver", .devinit = NULL, .id_table = nvme_pci_driver_id, .drv_flags = RTE_PCI_DRV_NEED_MAPPING, }; static inline int nvme_driver_register_dev_init(pci_driver_init fn_t) { int rc; nvme_rte_driver.devinit = fn_t; rte_eal_pci_register(&nvme_rte_driver); rc = rte_eal_pci_probe(); rte_eal_pci_unregister(&nvme_rte_driver); return rc; } #endif /* !USE_PCIACCESS */ typedef pthread_mutex_t nvme_mutex_t; Loading