Commit 36a793ad authored by Ben Walker's avatar Ben Walker Committed by Jim Harris
Browse files

nvme: Add a quirk to delay before enabling 



It has been discovered that some devices require
a very small delay before writing CC.EN to 1 after
CSTS.RDY goes to 0.

Change-Id: I73d31726d17ebf5bbec7ee528e2f98fcd05234dd
Signed-off-by: default avatarBen Walker <benjamin.walker@intel.com>
parent 652d48d5

lib/nvme/nvme_ctrlr.c

+20 −20
Original line number Diff line number Diff line
@@ -483,8 +483,10 @@ nvme_ctrlr_state_string(enum nvme_ctrlr_state state) 
		return "disable and wait for CSTS.RDY = 1";

	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:

		return "disable and wait for CSTS.RDY = 0";

	case NVME_CTRLR_STATE_ENABLE:

		return "enable controller by writing CC.EN = 1";

	case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:

		return "enable and wait for CSTS.RDY = 1";

		return "wait for CSTS.RDY = 1";

	case NVME_CTRLR_STATE_READY:

		return "ready";

	}
@@ -1167,21 +1169,10 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) 
		} else {

			if (csts.bits.rdy == 1) {

				SPDK_TRACELOG(SPDK_TRACE_NVME, "CC.EN = 0 && CSTS.RDY = 1 - waiting for shutdown to complete\n");

				/*

				 * Controller is in the process of shutting down.

				 * We need to wait for RDY to become 0.

				 */

				nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);

				return 0;

			}



			/*

			 * Controller is currently disabled. We can jump straight to enabling it.

			 */

			SPDK_TRACELOG(SPDK_TRACE_NVME, "CC.EN = 0 && CSTS.RDY = 0 - enabling controller\n");

			rc = nvme_ctrlr_enable(ctrlr);

			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);

			return rc;

			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);

			return 0;

		}

		break;
@@ -1203,14 +1194,23 @@ nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) 


	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:

		if (csts.bits.rdy == 0) {

			SPDK_TRACELOG(SPDK_TRACE_NVME, "CC.EN = 0 && CSTS.RDY = 0 - enabling controller\n");

			/* CC.EN = 0 && CSTS.RDY = 0, so we can enable the controller now. */

			SPDK_TRACELOG(SPDK_TRACE_NVME, "CC.EN = 0 && CSTS.RDY = 0\n");

			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);



			if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_ENABLE) {

				SPDK_TRACELOG(SPDK_TRACE_NVME, "Applying quirk: Delay 100us before enabling.\n");

				ctrlr->sleep_timeout_tsc = spdk_get_ticks() + spdk_get_ticks_hz() / 10000;

			}



			return 0;

		}

		break;



	case NVME_CTRLR_STATE_ENABLE:

		SPDK_TRACELOG(SPDK_TRACE_NVME, "Setting CC.EN = 1\n");

		rc = nvme_ctrlr_enable(ctrlr);

		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);

		return rc;

		}

		break;



	case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:

		if (csts.bits.rdy == 1) {

lib/nvme/nvme_internal.h

+12 −0
Original line number Diff line number Diff line
@@ -89,6 +89,13 @@ 
 */

#define NVME_INTEL_QUIRK_STRIPING 0x8



/*

 * A small delay is required before re-enabling a controller.

 * The delay required is often vanishingly small, such that

 * many drivers do not ever encounter the problem.

 */

#define NVME_QUIRK_DELAY_BEFORE_ENABLE 0x10



#define NVME_MAX_ASYNC_EVENTS	(8)



#define NVME_MIN_TIMEOUT_PERIOD		(5)
@@ -309,6 +316,11 @@ enum nvme_ctrlr_state { 
	 */

	NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0,



	/**

	 * Enable the controller by writing CC.EN to 1

	 */

	NVME_CTRLR_STATE_ENABLE,



	/**

	 * Waiting for CSTS.RDY to transition from 0 to 1 after enabling the controller.

	 */

lib/nvme/nvme_quirks.c

+2 −1
Original line number Diff line number Diff line
@@ -42,7 +42,8 @@ static const struct nvme_quirk nvme_quirks[] = { 
	{	{SPDK_PCI_VID_INTEL, 0x0953, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},

		NVME_INTEL_QUIRK_READ_LATENCY |

		NVME_INTEL_QUIRK_WRITE_LATENCY |

		NVME_INTEL_QUIRK_STRIPING

		NVME_INTEL_QUIRK_STRIPING |

		NVME_QUIRK_DELAY_BEFORE_ENABLE

	},

	{	{SPDK_PCI_VID_INTEL, 0x0A53, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},

		NVME_INTEL_QUIRK_STRIPING

test/lib/nvme/unit/nvme_ctrlr_c/nvme_ctrlr_ut.c

+84 −3
Original line number Diff line number Diff line
@@ -403,10 +403,15 @@ test_nvme_ctrlr_init_en_1_rdy_0(void) 


	/*

	 * Transition to CSTS.RDY = 0.

	 * init() should set CC.EN = 1.

	 */

	g_ut_nvme_regs.csts.bits.rdy = 0;

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);



	/*

	 * Transition to CC.EN = 1

	 */

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
@@ -444,10 +449,15 @@ test_nvme_ctrlr_init_en_1_rdy_1(void) 


	/*

	 * Transition to CSTS.RDY = 0.

	 * init() should set CC.EN = 1.

	 */

	g_ut_nvme_regs.csts.bits.rdy = 0;

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);



	/*

	 * Transition to CC.EN = 1

	 */

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
@@ -491,6 +501,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
@@ -516,6 +530,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -540,6 +558,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -564,6 +586,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -589,6 +615,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
@@ -634,6 +664,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
@@ -660,6 +694,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
@@ -685,6 +723,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -709,6 +751,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -734,6 +780,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR);
@@ -778,6 +828,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR);
@@ -803,6 +857,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -828,6 +886,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
@@ -853,6 +915,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 
	ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1;



	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0);
@@ -878,6 +944,10 @@ test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 


	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS);
@@ -911,6 +981,12 @@ test_nvme_ctrlr_init_en_0_rdy_0(void) 
	SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0);

	ctrlr.cdata.nn = 1;

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);



	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);



	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);
@@ -947,10 +1023,15 @@ test_nvme_ctrlr_init_en_0_rdy_1(void) 


	/*

	 * Transition to CSTS.RDY = 0.

	 * init() should set CC.EN = 1.

	 */

	g_ut_nvme_regs.csts.bits.rdy = 0;

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);



	/*

	 * Transition to CC.EN = 1

	 */

	CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0);

	CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);

	CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1);