Commit 2d686707 authored by Xue Liu's avatar Xue Liu Committed by Jim Harris
Browse files

barrier: LOONGARCH memory barriers 



Implement memory barrier for LOONGARCH platforms.

Change-Id: I44f5e63e6eb3f8bf98e965a22fb86f94e727061d
Signed-off-by: default avatarXue Liu <liuxue@loongson.cn>
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/16082


Community-CI: Mellanox Build Bot
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarChangpeng Liu <changpeng.liu@intel.com>
parent bae7cfb4

include/spdk/barrier.h

+10 −0
Original line number Diff line number Diff line
@@ -85,6 +85,16 @@ extern "C" { 
#define _spdk_smp_mb()	__asm__ __volatile__("fence rw, rw" ::: "memory")

#define _spdk_ivdt_dcache(pdata)



#elif defined(__loongarch__)



#define _spdk_rmb()	__asm volatile("dbar 0" ::: "memory")

#define _spdk_wmb()	__asm volatile("dbar 0" ::: "memory")

#define _spdk_mb()	__asm volatile("dbar 0" ::: "memory")

#define _spdk_smp_rmb()	__asm volatile("dbar 0" ::: "memory")

#define _spdk_smp_wmb()	__asm volatile("dbar 0" ::: "memory")

#define _spdk_smp_mb()	__asm volatile("dbar 0" ::: "memory")

#define _spdk_ivdt_dcache(pdata)



#else



#define _spdk_rmb()