Commit 241ce66d authored by liucheng74's avatar liucheng74 Committed by Jim Harris
Browse files

nvme/pcie: check CAP.CMBS to confirm whether the NVMe controller 


supports CMB

if the controller does not support CMB by setting CAP.CMBS to ‘0’,
nvme_pcie_ctrlr_map_cmb shoule exit instead of continuing.
Because vtophys_iommu_map_dma_bar in spdk_pci_device_map_bar will
insert wrong dma_map into g_vfio.maps.
it will cause DMA mapping failures and DMA unmapping failures

Change-Id: I40b8566726883b55e4ddcab43263baee784853b9
Signed-off-by: default avatarliucheng74 <liuc@yusur.tech>
Reviewed-on: https://review.spdk.io/c/spdk/spdk/+/26164


Community-CI: Mellanox Build Bot
Reviewed-by: default avatarJim Harris <jim.harris@nvidia.com>
Tested-by: default avatarSPDK Automated Test System <spdkbot@gmail.com>
Reviewed-by: default avatarChangpeng Liu <changpeliu@tencent.com>
parent 1968d804

lib/nvme/nvme_pcie.c

+4 −0
Original line number Diff line number Diff line
@@ -326,6 +326,10 @@ nvme_pcie_ctrlr_map_cmb(struct nvme_pcie_ctrlr *pctrlr) 
	union spdk_nvme_cmbloc_register cmbloc;

	uint64_t size, unit_size, offset, bar_size = 0, bar_phys_addr = 0;



	if (!pctrlr->regs->cap.bits.cmbs) {

		goto exit;

	}



	if (nvme_pcie_ctrlr_get_cmbsz(pctrlr, &cmbsz) ||

	    nvme_pcie_ctrlr_get_cmbloc(pctrlr, &cmbloc)) {

		SPDK_ERRLOG("get registers failed\n");

test/unit/lib/nvme/nvme_pcie.c/nvme_pcie_ut.c

+4 −0
Original line number Diff line number Diff line
@@ -785,6 +785,7 @@ test_nvme_pcie_ctrlr_map_unmap_cmb(void) 
	volatile struct spdk_nvme_registers regs = {};

	union spdk_nvme_cmbsz_register cmbsz = {};

	union spdk_nvme_cmbloc_register cmbloc = {};

	union spdk_nvme_cap_register cap = {};

	struct dev_mem_resource cmd_res = {};

	int rc;
@@ -799,11 +800,14 @@ test_nvme_pcie_ctrlr_map_unmap_cmb(void) 
	cmbsz.bits.sqs = 0;

	cmbloc.bits.bir = 0;

	cmbloc.bits.ofst = 100;

	cap.bits.cmbs = 1;



	nvme_pcie_ctrlr_set_reg_4(&pctrlr.ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),

				  cmbsz.raw);

	nvme_pcie_ctrlr_set_reg_4(&pctrlr.ctrlr, offsetof(struct spdk_nvme_registers, cmbloc.raw),

				  cmbloc.raw);

	nvme_pcie_ctrlr_set_reg_8(&pctrlr.ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),

				  cap.raw);



	nvme_pcie_ctrlr_map_cmb(&pctrlr);

	CU_ASSERT(pctrlr.cmb.bar_va == (void *)0x7f7c0080d000);