Commit 0568555a authored by Evgeniy Kochetov's avatar Evgeniy Kochetov Committed by Tomasz Zawadzki
Browse files

nvme: Add 'rdma_cm_event_timeout_ms' transport option 



Kernel NVMf RDMA target may be slow to respond and default 1 second
RDMA CM event timeout is not always enough. This patch allows to
configure RDMA CM event timeout.

Signed-off-by: default avatarEvgeniy Kochetov <evgeniik@nvidia.com>
Change-Id: I28a16d37b0a8be7dff529ff04e97703c393a045f
Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/21653


Reviewed-by: default avatarTomasz Zawadzki <tomasz.zawadzki@intel.com>
Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
Reviewed-by: default avatarAleksey Marchuk <alexeymar@nvidia.com>
Community-CI: Mellanox Build Bot
parent 967ed8a7

include/spdk/nvme.h

+8 −1
Original line number Diff line number Diff line 
/*   SPDX-License-Identifier: BSD-3-Clause

 *   Copyright (C) 2015 Intel Corporation. All rights reserved.

 *   Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.

 *   Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 *   Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 *   Copyright (c) 2023 Samsung Electronics Co., Ltd. All rights reserved.

 */
@@ -4279,6 +4279,13 @@ struct spdk_nvme_transport_opts { 
	 * It is zero, which means unlimited, by default.

	 */

	uint32_t rdma_max_cq_size;



	/**

	 * It is used for RDMA transport.

	 *

	 * RDMA CM event timeout in milliseconds.

	 */

	uint16_t rdma_cm_event_timeout_ms;

};

SPDK_STATIC_ASSERT(sizeof(struct spdk_nvme_transport_opts) == 24, "Incorrect size");

lib/nvme/nvme_rdma.c

+3 −6
Original line number Diff line number Diff line 
/*   SPDX-License-Identifier: BSD-3-Clause

 *   Copyright (C) 2016 Intel Corporation. All rights reserved.

 *   Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved.

 *   Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 *   Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 */



/*
@@ -40,9 +40,6 @@ 
/* number of STAILQ entries for holding pending RDMA CM events. */

#define NVME_RDMA_NUM_CM_EVENTS			256



/* CM event processing timeout */

#define NVME_RDMA_QPAIR_CM_EVENT_TIMEOUT_US	1000000



/* The default size for a shared rdma completion queue. */

#define DEFAULT_NVME_RDMA_CQ_SIZE		4096
@@ -639,8 +636,8 @@ nvme_rdma_process_event_start(struct nvme_rdma_qpair *rqpair, 


	rqpair->expected_evt_type = evt;

	rqpair->evt_cb = evt_cb;

	rqpair->evt_timeout_ticks = (NVME_RDMA_QPAIR_CM_EVENT_TIMEOUT_US * spdk_get_ticks_hz()) /

				    SPDK_SEC_TO_USEC + spdk_get_ticks();

	rqpair->evt_timeout_ticks = (g_spdk_nvme_transport_opts.rdma_cm_event_timeout_ms * 1000 *

				     spdk_get_ticks_hz()) / SPDK_SEC_TO_USEC + spdk_get_ticks();



	return 0;

}

lib/nvme/nvme_transport.c

+4 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 *   Copyright (C) 2016 Intel Corporation.

 *   All rights reserved.

 *   Copyright (c) 2021 Mellanox Technologies LTD. All rights reserved.

 *   Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 *   Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 */



/*
@@ -28,6 +28,7 @@ int g_current_transport_index = 0; 
struct spdk_nvme_transport_opts g_spdk_nvme_transport_opts = {

	.rdma_srq_size = 0,

	.rdma_max_cq_size = 0,

	.rdma_cm_event_timeout_ms = 1000

};



const struct spdk_nvme_transport *
@@ -824,6 +825,7 @@ spdk_nvme_transport_get_opts(struct spdk_nvme_transport_opts *opts, size_t opts_ 


	SET_FIELD(rdma_srq_size);

	SET_FIELD(rdma_max_cq_size);

	SET_FIELD(rdma_cm_event_timeout_ms);



	/* Do not remove this statement, you should always update this statement when you adding a new field,

	 * and do not forget to add the SET_FIELD statement for your added field. */
@@ -852,6 +854,7 @@ spdk_nvme_transport_set_opts(const struct spdk_nvme_transport_opts *opts, size_t 


	SET_FIELD(rdma_srq_size);

	SET_FIELD(rdma_max_cq_size);

	SET_FIELD(rdma_cm_event_timeout_ms);



	g_spdk_nvme_transport_opts.opts_size = opts->opts_size;

module/bdev/nvme/bdev_nvme.c

+6 −1
Original line number Diff line number Diff line
@@ -5543,7 +5543,8 @@ bdev_nvme_set_opts(const struct spdk_bdev_nvme_opts *opts) 
	}



	if (opts->rdma_srq_size != 0 ||

	    opts->rdma_max_cq_size != 0) {

	    opts->rdma_max_cq_size != 0 ||

	    opts->rdma_cm_event_timeout_ms != 0) {

		struct spdk_nvme_transport_opts drv_opts;



		spdk_nvme_transport_get_opts(&drv_opts, sizeof(drv_opts));
@@ -5553,6 +5554,9 @@ bdev_nvme_set_opts(const struct spdk_bdev_nvme_opts *opts) 
		if (opts->rdma_max_cq_size != 0) {

			drv_opts.rdma_max_cq_size = opts->rdma_max_cq_size;

		}

		if (opts->rdma_cm_event_timeout_ms != 0) {

			drv_opts.rdma_cm_event_timeout_ms = opts->rdma_cm_event_timeout_ms;

		}



		ret = spdk_nvme_transport_set_opts(&drv_opts, sizeof(drv_opts));

		if (ret) {
@@ -8044,6 +8048,7 @@ bdev_nvme_opts_config_json(struct spdk_json_write_ctx *w) 
	spdk_json_write_named_bool(w, "io_path_stat", g_opts.io_path_stat);

	spdk_json_write_named_bool(w, "allow_accel_sequence", g_opts.allow_accel_sequence);

	spdk_json_write_named_uint32(w, "rdma_max_cq_size", g_opts.rdma_max_cq_size);

	spdk_json_write_named_uint16(w, "rdma_cm_event_timeout_ms", g_opts.rdma_cm_event_timeout_ms);

	spdk_json_write_object_end(w);



	spdk_json_write_object_end(w);

module/bdev/nvme/bdev_nvme.h

+2 −1
Original line number Diff line number Diff line 
/*   SPDX-License-Identifier: BSD-3-Clause

 *   Copyright (C) 2016 Intel Corporation. All rights reserved.

 *   Copyright (c) 2019 Mellanox Technologies LTD. All rights reserved.

 *   Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 *   Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 *   Copyright (c) 2022 Dell Inc, or its subsidiaries. All rights reserved.

 */
@@ -298,6 +298,7 @@ struct spdk_bdev_nvme_opts { 
	bool io_path_stat;

	bool allow_accel_sequence;

	uint32_t rdma_max_cq_size;

	uint16_t rdma_cm_event_timeout_ms;

};



struct spdk_nvme_qpair *bdev_nvme_get_io_qpair(struct spdk_io_channel *ctrlr_io_ch);