Commit 04df6e69 authored by Kefu Chai's avatar Kefu Chai Committed by Ben Walker
Browse files

barrier.h: fix load fence on armv8 

the weak memory ordering on armv8 can be implemented using

dsb ld

see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/DMB.html



Change-Id: I4db34b87fa659967109adc688cad784018cedaae
Signed-off-by: default avatarKefu Chai <tchaikov@gmail.com>
Reviewed-on: https://review.gerrithub.io/430767


Tested-by: default avatarSPDK CI Jenkins <sys_sgci@intel.com>
Chandler-Test-Pool: SPDK Automated Test System <sys_sgsw@intel.com>
Reviewed-by: default avatarJim Harris <james.r.harris@intel.com>
Reviewed-by: default avatarBen Walker <benjamin.walker@intel.com>
parent d853ced6

include/spdk/barrier.h

+1 −1
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ extern "C" { 
#ifdef __PPC64__

#define spdk_rmb()	__asm volatile("sync" ::: "memory")

#elif defined(__aarch64__)

#define spdk_rmb()	__asm volatile("dsb lt" ::: "memory")

#define spdk_rmb()	__asm volatile("dsb ld" ::: "memory")

#elif defined(__i386__) || defined(__x86_64__)

#define spdk_rmb()	__asm volatile("lfence" ::: "memory")

#else